In large high-performance very large scale integration (VLSI) chips, an internal clock signal is distributed throughout the chip to control timing of the chip as a function of an external system clock. The internal clock signal is typically generated from the external clock by a clock buffer circuit, and then distributed to the end circuits in the chip through some form of on-chip clock distribution network. However, in the clock distribution network resistance and inductance of the transmission lines can limit the distribution of the clock signal throughout the VLSI chip. Thus, it would be advantageous to counter the transmission line signal loss of a clock signal in a VLSI chip.